Thermal and stress gradient based RC extraction, timing and power analysis

ABSTRACT

Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.

BACKGROUND

1. Field

Aspects of the present disclosure relate generally to the field ofelectronic devices, and more particularly, to circuit analysistechniques.

2. Background

As technology scaling progresses, the costs are increasing. Threedimensional (3D) technology based on through vias can significantlyimprove circuit performance and density. However, heat dissipation is amajor challenge. Because of stacking and/or circuit density, there is alarge temperature variation across the chip which may produce extensivelocalized heating. Device electrical parameters, such as resistance,capacitance, carrier mobility, threshold voltage, electromigration, andsub-threshold leakage current, are all functions of temperature. Thus, aneed exists for identifying and quantifying the temperature variation.Similarly, because carrier mobility is a function of stress, a need alsoexists for identifying and quantifying the stress variation.

Conventionally, temperature variation and stress variation across thechip area are not considered during the circuit design process. Forexample, timing and power analysis are performed without considering theimpact of stress. As for temperature, timing and power analysis occursat pre-defined corners of the chip where the temperature is selected aseither a maximum value or a minimum value. That selected value isassumed for all circuits on the chip. As such, the circuits at theregions of thermal or stress hot spots are not properly characterizedduring design, possibly leading to circuit failure upon manufacture.

SUMMARY

According to one aspect, a range of temperature and stress values ofeach of many windows located across the circuit is analyzed. Based onthese temperature and stress values, the resistance capacitance (RC)parasitic values of individual windows are calculated.

In another aspect, an apparatus includes means for analyzing a range oftemperature values and a range of stress values for each of a pluralityof window locations across a circuit layout. The apparatus also includesmeans for calculating window location specific resistance capacitance(RC) parasitic values based on the analyzed temperature and stressvalues of each corresponding window location.

In yet another aspect, a computer readable medium records program code.The program code includes program code to analyze a range of temperatureand stress values of each of many windows locations across the circuit.The program code also includes program code to calculate the resistancecapacitance (RC) parasitic values of individual windows, based on theanalyzed temperature and stress values.

In still another aspect, a method includes the step of analyzing a rangeof temperature values and a range of stress values for each of aplurality of window locations across a circuit layout. The method alsoincludes the step of calculating window location specific resistancecapacitance (RC) parasitic values based on the analyzed temperature andstress values of each corresponding window location.

In a further aspect, an apparatus for circuit layout analysis includes amemory and at least one processor coupled to the memory. Theprocessor(s) is configured to analyze a range of temperature values anda range of stress values for each of a group of window locations acrossa circuit layout. The processor(s) is also configured to calculatewindow location specific resistance capacitance (RC) parasitic valuesbased on the analyzed temperature and stress values of a correspondingwindow location.

This has outlined, rather broadly, the features and technical advantagesof the present disclosure in order that the detailed description thatfollows may be better understood. Additional features and advantages ofthe disclosure will be described below. It should be appreciated bythose skilled in the art that this disclosure may be readily utilized asa basis for modifying or designing other structures for carrying out thesame purposes of the present disclosure. It should also be realized bythose skilled in the art that such equivalent constructions do notdepart from the teachings of the disclosure as set forth in the appendedclaims. The novel features, which are believed to be characteristic ofthe disclosure, both as to its organization and method of operation,together with further objects and advantages, will be better understoodfrom the following description when considered in connection with theaccompanying figures. It is to be expressly understood, however, thateach of the figures is provided for the purpose of illustration anddescription only and is not intended as a definition of the limits ofthe present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, nature, and advantages of the present disclosure willbecome more apparent from the detailed description set forth below whentaken in conjunction with the drawings in which like referencecharacters identify correspondingly throughout.

FIG. 1A is a flow diagram conceptually illustrating the presentdisclosure.

FIG. 1B is a flow diagram conceptually illustrating the presentdisclosure.

FIG. 2 is a block diagram illustrating exemplary window locations on acircuit layout according to the present disclosure.

FIG. 3 is a block diagram illustrating a top view of an exemplarystacked die according to one aspect of the present disclosure.

FIG. 4 is a block diagram showing an exemplary wireless communicationsystem in which an embodiment of the disclosure may be advantageouslyemployed.

FIG. 5 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of a semiconductor component accordingto one embodiment.

DETAILED DESCRIPTION

According to an aspect of the present disclosure, temperature and stressvariations across a chip are accounted for when analyzing the chip.Accordingly, resistance and capacitance are more accurately modeled,leading to more precise timing and power analyses of circuits on thechip.

An exemplary operation of the present disclosure is illustrated in FIG.1A. At block 100, a chip containing the circuits to be analyzed isidentified. Input of the layout of the circuits on the whole chip occursat block 102. In one embodiment, the input layout is in the form of aGDSII file.

At block 104, thermal analysis is performed. In one embodiment, theanalysis may use a finite element solver or compact model. From thethermal analysis, peak temperature values and each correspondinglocation is obtained at block 106. A location based temperature file isthen generated, at block 108, from the results of the thermal analysisby obtaining the average of peak temperatures within each individualwindow location on the layout.

As seen in FIG. 2, the windows 202 are regions of the chip layout 200and may be of any size desired or selected by the user (e.g., 5 micronby 5 micron). That is, the entire chip layout 200 is divided intowindows 202 so that analyses can occur at each window, rather than beingbased on general conditions of the entire chip.

Returning to FIG. 1A, at block 110, a stress analysis is performed onthe circuit layout. Based on the analysis peak stress values areobtained, as well as corresponding locations at block 112. At block 114,a location based stress file is generated by obtaining the average ofpeak stress values within each individual window location on the layout.

The location based temperature and stress files can be used to obtainmore accurate characterization of circuits in the chip layout. Forexample, at block 116 resistance capacitance (RC) parasitic extractionat each of the individual window locations is performed. The resistanceand capacitance are calculated using data from the location basedtemperature and stress files, and either a well defined equation or acalibrated look up table. As such, the temperature and stress variationaware RC extraction is obtained.

For static timing analysis, standard cells are characterized at a rangeof temperatures and stresses. At block 118, propagation delays andtransition times for standard cells are characterized and represented ina look up table using temperature and stress as variables (e.g., .LIBfiles). At block 120, the temperature and stress variation aware timingof the circuit layout (i.e., set up and hold times) is derived based onthe temperature and stress variation aware RC extraction, temperatureand stress dependent propagation delay and transition time, and thelocation based temperature and stress files. When the timing of thecircuit layout is calculated, the temperature and stress variation awareparasitic RC values are used. With the location based temperature andstress files, the corresponding values of the propagation delays andtransition times are obtained for each standard cell at a specificlocation within the layout.

The location based temperature and stress files can also improve poweranalysis because sub-threshold leakage current is a function of carriermobility and threshold voltage. For example, at block 122, leakagecurrent for standard cells and/or gates is characterized at a range oftemperatures and stresses, resulting in temperature and stress variationaware leakage current (e.g., .LIB files). At block 124, the temperatureand stress variation aware power consumption of the circuit layout isderived based on the temperature and stress variation aware RCextraction, and leakage current (122), the propagation delay andtransition time (118), the location based temperature file (108) and thelocation based stress file (114).

Based on the temperature and stress variation aware timing and poweranalyses, the overall circuit layout can be evaluated. For example, theanalyses could be compared to desired timing and power performance forthat circuit layout. If it passes, then further development of the chipcould occur. On the other hand, if it fails, then the circuit will needto be modified and the process could be repeated on the new circuitdesign.

Another exemplary operation of the present disclosure is illustrated inFIG. 1B in which simulation program with integrated circuit emphasis(SPICE) simulation occurs. After the temperature and stress variationaware RC extractions are obtained at block 116, they are imported backto a circuit netlist (223). The circuit netlist and a SPICE model (222),and the location based temperature file (108), and the location basedstress file (104) then applied to a temperature and stress variationaware SPICE simulation (224) to analyze the circuit layout.

According to one embodiment of the present disclosure, for 3D integratedcircuits (ICs) (i.e., stacked tiers, in which at least one of the tiersincludes through vias), the location and stress based temperatureprofiles of a circuit layout of a first die/tier can be imported toanother die/tier within the same stack. FIG. 3 illustrates a top view ofa 3D IC in which a die 300 of tier 2 is stacked on top of a die 302 ontier 1. Within the area where the circuit layouts of die 300 and die 302overlap with each other, there is no method of creating location basedtemperature and stress files while considering two separate layouts fromtwo dies. After creating location based temperature and stress profilesfor the circuit layout of the die 300 of tier 2, the temperature andstress values of each individual window location 304 in the overlap areaof the die 302 in tier 2 may be used for the corresponding individuallocation window in the same overlap area on the layout of other tier(tier 1).

Thus, it can be seen that thermal and stress gradient profiles of a chiplayout can be used to improve timing and power analyses of that layout.

FIG. 4 is a block diagram showing an exemplary wireless communicationsystem 400 in which an embodiment of the disclosure may beadvantageously employed. For purposes of illustration, FIG. 4 showsthree remote units 420, 430, and 450 and two base stations 440. It willbe recognized that wireless communication systems may have many moreremote units and base stations. Remote units 420, 430, and 450 includeIC devices 425A, 425C and 425B, designed using the timing and poweranalyses based on thermal and stress gradient. It will be recognizedthat any device containing an IC may also be designed using the timingand power analysis based on thermal and stress gradient disclosed here,including the base stations, switching devices, and network equipment.FIG. 4 shows forward link signals 480 from the base station 440 to theremote units 420, 430, and 450 and reverse link signals 490 from theremote units 420, 430, and 450 to base stations 440.

In FIG. 4, remote unit 420 is shown as a mobile telephone, remote unit430 is shown as a portable computer, and remote unit 450 is shown as afixed location remote unit in a wireless local loop system. For example,the remote units may be mobile phones, hand-held personal communicationsystems (PCS) units, portable data units such as personal dataassistants, GPS enabled devices, navigation devices, set top boxes,music players, video players, entertainment units, fixed location dataunits such as meter reading equipment, or any other device that storesor retrieves data or computer instructions, or any combination thereof.Although FIG. 4 illustrates remote units according to the teachings ofthe disclosure, the disclosure is not limited to these exemplaryillustrated units. Embodiments of the disclosure may be suitablyemployed for any device designed with thermal and stress gradient basedanalyses.

FIG. 5 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of a semiconductor component,employing thermal and stress gradient based timing and power analyses asdisclosed above. A design workstation 500 includes a hard disk 501containing operating system software, support files, and design softwaresuch as Cadence or OrCAD. The design workstation 500 also includes adisplay to facilitate design of a circuit 510 or a semiconductorcomponent 512 such as a circuit layout wherein timing and power analysisare performed based on the thermal and stress gradient. A storage medium504 is provided for tangibly storing the circuit design 510 or thesemiconductor component 512. The circuit design 510 or the semiconductorcomponent 512 may be stored on the storage medium 504 in a file formatsuch as GDSII or GERBER. The storage medium 504 may be a CD-ROM, DVD,hard disk, flash memory, or other appropriate device. Furthermore, thedesign workstation 500 includes a drive apparatus 503 for acceptinginput from or writing output to the storage medium 504.

Data recorded on the storage medium 504 may specify logic circuitconfigurations, pattern data for photolithography masks, or mask patterndata for serial write tools such as electron beam lithography. The datamay further include logic verification data such as timing diagrams ornet circuits associated with logic simulations. Providing data on thestorage medium 504 facilitates the design of the circuit design 510 orthe semiconductor component 512 by decreasing the number of processesfor designing semiconductor wafers.

For a firmware and/or software implementation, the methodologies may beimplemented with modules (e.g., procedures, functions, and so on) thatperform the functions described herein. Any machine-readable mediumtangibly embodying instructions may be used in implementing themethodologies described herein. For example, software codes may bestored in a memory and executed by a processor unit. Memory may beimplemented within the processor unit or external to the processor unit.As used herein the term “memory” refers to any type of long term, shortterm, volatile, nonvolatile, or other memory and is not to be limited toany particular type of memory or number of memories, or type of mediaupon which memory is stored.

If implemented in firmware and/or software, the functions may be storedas one or more instructions or code on a computer-readable medium.Examples include computer-readable media encoded with a data structureand computer-readable media encoded with a computer program.Computer-readable media includes physical computer storage media. Astorage medium may be any available medium that can be accessed by acomputer. By way of example, and not limitation, such computer-readablemedia can comprise RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, malefic disk storage or other magnetic storage devices, or anyother medium that can be used to store desired program code in the formof instructions or data structures and that can be accessed by acomputer; disk and disc, as used herein, includes compact disc (CD),laser disc, optical disc, digital versatile disc (MD), floppy disk andblu-ray disc where disks usually reproduce data magnetically, whilediscs reproduce data optically with lasers. Combinations of the aboveshould also be included within the scope of computer-readable media.

In addition to storage on computer readable medium, instructions and/ordata may be provided as signals on transmission media included in acommunication apparatus. For example, a communication apparatus mayinclude a transceiver having signals indicative of instructions anddata. The instructions and data are configured to cause one or moreprocessors to implement the functions outlined in the claims.

Although specific circuitry has been set forth, it will be appreciatedby those skilled in the art that not all of the disclosed circuitry isrequired to practice the disclosure. Moreover, certain well knowncircuits have not been described, to maintain focus on the disclosure.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the technologyof the disclosure as defined by the appended claims. For example,relational terms, such as “above” and “below” are used with respect to asubstrate or electronic device. Of course, if the substrate orelectronic device is inverted, above becomes below, and vice versa.Additionally, if oriented sideways, above and below may refer to sidesof a substrate or electronic device. Moreover, the scope of the presentapplication is not intended to be limited to the particular embodimentsof the process, machine, manufacture, composition of matter, means,methods and steps described in the specification. As one of ordinaryskill in the art will readily appreciate from the disclosure, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present disclosure. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed is:
 1. A method of circuit layout analysis, comprising:analyzing a range of temperature values and a range of stress values foreach of a plurality of regions across a circuit layout; and calculatingregion specific resistance capacitance (RC) parasitic values for eachregion in the plurality of regions across the circuit layout based onthe analyzed temperature and stress values of a corresponding region inthe plurality of regions across the circuit layout.
 2. The method ofclaim 1, further comprising calculating timing values for the circuitlayout based on the calculated RC values, standard cell propagationdelay values and transition time values, and analyzed temperature andstress values of at least one region in the plurality of regions acrossthe circuit layout.
 3. The method of claim 1, further comprisingcalculating power values of the circuit layout based on the calculatedRC values, standard cell leakage current values, and analyzedtemperature and stress values of at least one region in the plurality ofregions across the circuit layout.
 4. The method of claim 1, furthercomprising importing the analyzed temperature values of individualregions in the plurality of regions of the circuit layout of one die tocorresponding regions of another die on a different tier of a 3Dintegrated circuit (IC).
 5. The method of claim 1, further comprisingsimulating the circuit layout with simulation program with integratedcircuit emphasis (SPICE), in accordance with the calculated RC values.6. The method of claim 1, further comprising integrating the circuitlayout into at least one of a mobile phone, a set top box, a musicplayer, a video player, an entertainment unit, a navigation device, acomputer, a hand-held personal communication systems (PCS) unit, aportable data unit, and a fixed location data unit.
 7. An apparatus forcircuit layout analysis, comprising: means for analyzing a range oftemperature values and a range of stress values for each of a pluralityof regions across a circuit layout; and means for calculating regionspecific resistance capacitance (RC) parasitic values for each region inthe plurality of regions across the circuit layout based on the analyzedtemperature and stress values of a corresponding region in the pluralityof regions across the circuit layout.
 8. The apparatus of claim 7,further comprising means for calculating timing values for the circuitlayout based on calculated RC values, standard cell propagation delayvalues and transition time values, and analyzed temperature and stressvalues of at least one region in the plurality of regions across thecircuit layout.
 9. The apparatus of claim 7, further comprising meansfor calculating power values of the circuit layout based on calculatedRC values, standard cell leakage current values, and analyzedtemperature and stress values of at least one region in the plurality ofregions across the circuit layout.
 10. The apparatus of claim 7, furthercomprising means for importing the analyzed temperature values ofindividual regions in the plurality of regions of the circuit layout ofone die to corresponding regions of another die on a different tier of a3D integrated circuit (IC).
 11. The apparatus of claim 7, furthercomprising means for simulating the circuit layout with simulationprogram with integrated circuit emphasis (SPICE), in accordance withcalculated RC values.
 12. The apparatus of claim 7, further comprisingmeans for integrating the circuit layout into at least one of a mobilephone, a set top box, a music player, a video player, an entertainmentunit, a navigation device, a computer, a hand-held personalcommunication systems (PCS) unit, a portable data unit, and a fixedlocation data unit.
 13. A computer readable medium storingnon-transitory program code for circuit layout analysis, comprising:program code to analyze a range of temperature values and a range ofstress values for each of a plurality of regions across a circuitlayout; and program code to calculate region specific resistancecapacitance (RC) parasitic values for each region in the plurality ofregions across the circuit layout based on the analyzed temperature andstress values of a corresponding region in the plurality of regionsacross the circuit layout.
 14. The medium of claim 13, furthercomprising program code to calculate timing values for the circuitlayout based on the calculated RC values, standard cell propagationdelay values and transition time values, and analyzed temperature andstress values of at least one region in the plurality of regions acrossthe circuit layout.
 15. The medium of claim 13, further comprisingprogram code to calculate power values of the circuit layout based onthe calculated RC values, standard cell leakage current values, andanalyzed temperature and stress values of at least one region in theplurality of regions across the circuit layout.
 16. The medium of claim13, further comprising program code to import the analyzed temperaturevalues of individual regions in the plurality of regions of the circuitlayout of one die to corresponding regions of another die on a differenttier of a 3D integrated circuit (IC).
 17. The medium of claim 13,further comprising program code to simulate the circuit layout withsimulation program with integrated circuit emphasis (SPICE), inaccordance with the calculated RC values.
 18. The medium of claim 13,further comprising program code to integrate the circuit layout into atleast one of a mobile phone, a set top box, a music player, a videoplayer, an entertainment unit, a navigation device, a computer, ahand-held personal communication systems (PCS) unit, a portable dataunit, and a fixed location data unit.
 19. A method of circuit layoutanalysis, comprising: the step for analyzing a range of temperaturevalues and a range of stress values for each of a plurality of regionsacross a circuit layout; and the step for calculating window locationspecific resistance capacitance (RC) parasitic values for each region inthe plurality of regions across the circuit layout based on the analyzedtemperature and stress values of a corresponding region in the pluralityof regions across the circuit layout.
 20. The method of claim 19,further comprising the step of integrating the circuit layout into atleast one of a mobile phone, a set top box, a music player, a videoplayer, an entertainment unit, a navigation device, a computer, ahand-held personal communication systems (PCS) unit, a portable dataunit, and a fixed location data unit.
 21. An apparatus for circuitlayout analysis, comprising: a memory; and at least one processorcoupled to the memory and configured: to analyze a range of temperaturevalues and a range of stress values for each of a plurality of regionsacross a circuit layout; and to calculate region specific resistancecapacitance (RC) parasitic values for each region in the plurality ofregions across the circuit layout based on the analyzed temperature andstress values of a corresponding region in the plurality of regionsacross the circuit layout.
 22. The apparatus of claim 21, in which theprocessor is further configured to calculate timing values for thecircuit layout based on the calculated RC values, standard cellpropagation delay values and transition time values, and analyzedtemperature and stress values of at least one region in the plurality ofregions across the circuit layout.
 23. The apparatus of claim 21, inwhich the processor is further configured to calculate power values ofthe circuit layout based on the calculated RC values, standard cellleakage current values, and analyzed temperature and stress values of atleast one region in the plurality of regions across the circuit layout.24. The apparatus of claim 21, in which the processor is furtherconfigured to import the analyzed temperature values of individualregions in the plurality of regions of the circuit layout of one die tocorresponding regions of another die on a different tier of a 3Dintegrated circuit (IC).
 25. The apparatus of claim 21, in which theprocessor is further configured to simulate the circuit layout withsimulation program with integrated circuit emphasis (SPICE), inaccordance with the calculated RC values.
 26. The apparatus of claim 21,in which the processor is further configured to integrate the circuitlayout into at least one of a mobile phone, a set top box, a musicplayer, a video player, an entertainment unit, a navigation device, acomputer, a hand-held personal communication systems (PCS) unit, aportable data unit, and a fixed location data unit.